Logic gate

ABSTRACT

A logic circuit having a first multiemitter transistor each of whose emitters is connected to a different input terminal and whose collector is connected to a junction point. A second transistor, whose conduction is controlled by means of a plurality of diodes coupled between its base and a different one of the input terminals, has its emitter connected to the base of the first transistor. For one operating condition the emitter-tobase junctions of the first transistor as well as the diodes are reverse biased and the second transistor provides a high transient current followed by a lower steady state current, through the base-to-collector junction of the first transistor, into the junction point. For another operating condition at least one of the emitter-to-base junctions of the first transistor as well as at least one of the diodes are forward biased and a transient current is provided to the base of the first transistor which then draws its collector current out of the junction point.

United States Patent Gamble I [54] LOGIC GATE Primary Examiner-Donald D.Forrer Assistant Examiner-David M. Carter ABSTRACT A logic circuithaving a first multiemitter transistor each of whose emitters isconnected to a different input terminal and whose collector is connectedto a junction point. A second transistor, whose conduction is controlledby means of a plurality of diodes coupled between its base and adifferent one of the input terminals, has its emitter connected to thebase of the first transistor. For one operating condition theemitter-tobase junctions of the first transistor as well as the diodesare reverse biased and the second transistor provides a high transientcurrent followed by a lower steady state current, through thebase-to-collector junction of the first transistor, into the junctionpoint. For another operating condition at least one of theemitter-to-base junctions of the first transistor as well as at leastone of the diodes are forward biased and a transient current is providedto the base of the first transistor which then draws its collectorcurrent out of the junction 10 Claims, 3 Drawing Figures [72] Inventor:Bernard Gamble, Granada Hills, Ammwy H. Christoffersen [73] Assignee:RCA Corporation [57] [22] Filed: Aug. 10, 1970 [21] Appl.No.: 62,399

[52] U.S.Cl ..307/2l5,307/2l6, 307/218, 307/299 A, 307/300 [51] Int. Cl..H03k l9/34,H03kl9/36 [58] FieldoiSearch ..307/2l6,215, 299A,300,2l8

[56] References Cited UNITED STATES PATENTS 3,351,782 11/1967 3,315,1004/1967 3,233,125 2/1966 3,083,303 3/1963 3,560,761 2/1971 point.3,473,047 10/1969 Bohn ..307/215 I J/ /6 42 t 44 L l 5; d5 2- i 4-\/\N\/ 6 f4 .9 i]

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mamas '8 me- SHEET 1 [IF 2 Fi/JA 4197' LOGIC GATE BACKGROUND OF THEINVENTION Digital circuits are used for performing logical operations incomputers and other data processing equipment. A type of digital circuitknown as transistor-transistor logic ('ITL) having good speed, power,and noise immunity characteristics, has become widely accepted.

Since their introduction, the performance of TTL circuits, a typicalexample of which is shown in FIG. 1, has improved due to the advances inprocessing technology. However, further improvement in the turn on timeis presently limited by shunt and stray capacitances, and especiallythose capacitances such as C S associated with the collector region ofthe input multiemitter transistors.

The effect of the R ,,C time constant can be understood by reference toFIG. 2, which is the schematic diagram of a commercially available highnoise immunity 'I'IL gate. The input threshold voltage has beenincreased by the addition of the collector-to-base diode of transistorQ23 between the emitter of transistor Q28 and the base of transistorQ24. The connection of the emitter of Q23 to the collector of Q20attempts to provide rapid removal of the stored base charge of Q24.However, the following disadvantages occurred due to these changes.

First, since the shunt capacitance (C present at the collector oftransistor Q20 must now be charged to a higher potential than in FIG. 1(due to the base-to-collector diode drop of transistor Q23), the inputcurrent must be increased (from 1.6 milliamperes to 4.0 milliamperes ina typical circuit) to achieve the same turn on time as in the circuit ofFIG. I. This input current increase is undesirable because it reducesthe fanout capacity of the circuit (from to 4 in a typical example).

Second, when the input signals go low and transistor Q24 is to be turnedoff, it is evident that the shunting paths existing across the base oftransistor Q24 include the series combination of the output impedance ofthe driving gate and the collector-to-emitter voltages of Q and Q23.Under normal operating condition, the potential required for current toflow through the shunting path exceeds that existing at the base of Q24and no advantage is gained.

It is an object of this invention to provide a circuit of the samegeneral class as those described above having improved noise immunity,without accompanying increase in power dissipation, or accompanyingreduction of fanout capability of sacrifice in speed.

SUMMARY OF THE INVENTION A logic circuit having a first multiemittertransistor, each of whose emitters is connected to a different inputterminal and whose collector is connected to a junction point. A secondtransistor, whose conduction is controlled by means of a plurality ofasymmetrically conducting devices, coupled between its base and adifferent one of the input terminals, has its emitter connected to thebase of the first transistor. For one condition of input signals, theemitter-to-base junctions of the first transistor as well as the devicesare reverse biased and the second transistor provides a current throughthe base-to-collector junction of the first transistor into the junctionpoint. For another input signal condition as least one of theemitterto-base junctions of the first transistor as well as at least oneof the devices are forward biased and a transient current is provided tothe base of the first transistor which then draws its collector currentout of the junction point.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of abasic TTL logic gate;

FIG. 2 is a schematic diagram of another TTL gate known in the art; and

FIG. 3 is a schematic diagram of a logic gate embodying the invention.

DESCRIPTION OF THE INVENTION CIRCUIT DESCRIPTION The two-input logiccircuit of FIG. 3 includes an input section which combines features ofdiode-transistor logic (D'IL) and transistor-transistor logic ('ITL).Some transistors in FIG. 3 are identified by numerical and alphabeticsubscripts. This is done to emphasize that all transistors having thesame numerical subscript may have the same collector diffusion.

The input section includes multiemitter transistor 06 having itscollector connected to the base of transistor 04A and each of itsemitter electrodes to a different one of the input terminals l4, l6.Capacitance C connected between the collector of transistor Q6 andground, is drawn with dashed lines to indicate that it is a distributedparameter. C s represents the collector-to-substrate capacitance oftransistor 06 as well as any other distributed and stray capacitanceassociated with that node. Capacitance C also drawn with dashed lines,includes the collector-to-base capacitance of transistor 06. The circuitmay have more than two input terminals and transistor Q6 may have morethan two emitters but for ease of illustration the drawing is solimited. Diode connected transistor Q7 which has its collector and baseconnected in common to terminal 12 and each of its two emitters to adifferent one of the input terminals (I4, 16) is provided to suppresspositive and negative going transients. Pullup resistors R6 and R7 areconnected between power supply terminal 10 and input terminals 16 and14, respectively. 1

As in DTL circuits, input diodes CR1 and CR2 have their cathodesconnected to terminals 16 and 14 respectively and their anodes connectedin common to the base of transistor QSA to which is also connected oneend of current source resistor R5. The other end of resistor R5 isconnected to positive power supply 10 so that current through resistorR5 is in a direction to forward bias the base-to-emitter junction oftransistor QSA and/0r diodes CR1 and CR2. The emitter of transistor QSAis connected to the base of transistor 06 and the collector oftransistor QSA is connected to the second emitterelectrode 2e ofcollector load (current) switching transistor Q2B. Transistor 058 hasits base connected to the emitter of transistor QSA and its collectorand emitter connected in common to the collector of transistor QSA. Thecapacitances associated with the collector-base and emitterbasejunctions of transistor QSB are thus connected in parallel across thecollector-to-emitter of transistor QSA.

The first emitter 1e of transistor Q2B is connected in com transistor02B and terminal 10 and the collectors of transistors Q28 and 02A areconnected to terminal 10. The collectors of transistors 04C and Q4A aswell as the collector and emitter of transistor 04B are connected to thebase of transistor QZB. The colIector-to-base as well as theemitter-tobase junctions of transistor Q4B are connected in parallelbetween the collector of transistor 04A and the base of transistor Q8.This, as explained below, provides AC coupling between the two points.The emitter of transistor 04A is connected to the collector of shuntbias transistor Q8 and the bases of transistors Q3 and QIA. The emittersof transistors 03, 01A and Q8 are connected to the negative power supplyterminal 12.

The collector of transistor 01A is connected to output terminal 20 towhich is also connected the base and collector of transistor 013, theemitter of transistor 04C, and one end of resistor R2. The other end ofresistor R2 is connected in common to the base of transistor Q4C and theemitter of transistor 02A. The combination of transistor 04C andresistor R2 provides current regulation and limits the output current toa safe value. The base electrodes of transistors Q18 and 04B areconnected in common to the base of transistor O8 to which is alsoconnected one end of resistor R1. The base of transistor O8 is thuscoupled by means of the junction capacitances of transistors Q43 and018, respectively, to the collector of transistor Q4A and to thecollector of transistor QIA.

A bias network to generate a relatively constant steady state shuntcurrent includes resistor R9 and R1 and transistors Q9 and Q8. ResistorR9 is connected between terminal 10 and the common connection of thebase and collector of diode connected transistor Q9. The emitter oftransistor Q9 is connected to terminal 12 and resistor R1 which controlsthe amount of base current into transistor O8 is connected between thebase of transistors Q9 and Q8.

CIRCUIT OPERATION The operation of the circuit is best understood byexamining the response of the circuit to a complete cycle of the inputwave form, i.e., (I) all signal inputs in the steady state highcondition; (2) transition of at least one input from the high to the lowcondition; (3) at least one input in the steady state low condition; (4)transition of all low inputs to the high condition. Assume for theremainder of this description that the magnitude of the potentialapplied between terminals l and 12 is approximately 5 volts and that thebase-toemitter voltage drop, V,,,;, of these transistors in the forwarddirection is approximately 0.75 volts.

I. Assume that the input signals applied to tenninals l4 and 16 are highwith each signal being 4 volts or more. Under this condition, a steadystate current flows through current source resistor R5, thebase-to-ernitter junction of transistor QSA, the base-to-collectorjunction of transistor Q6, into the base of transistor Q4A and,amplified, out of the emitter of transistor Q4A to provide the basecurrent for transistors Q3 and 01A, which are connected in parallel, andthe collector current for transistor Q8. If the potential at the base oftransistor Q3 and QlA is 0.75 volt, the voltage at the base oftransistor Q4A is 1.5 volts, the voltage at the base of transistor 06 is2.25 volts and the voltage at the base of transistor QSA is 3 volts.Since the input signals applied at terminals 14 and 16 are assumed to beat least 4 volts, diodes CR1 and CR2 are reverse biased. In addition,the multiple emitter-to-base junctions of transistor Q6 are also reversebiased since the base is at 2.25 volts while the emitters are at leastat 4 volts.

Transistor Q4A is operated as a phase splitter, amplifying the basecurrent supplied to its base and generating in response thereto anin-phase signal at the emitter and an outof-phase signal at thecollector. In the all inputs high" steady state condition, transistorQ4A is saturated since its forward current transfer ratio (B) exceedsthe ratio of available collector current (I to available base current (IIn other words, BXI is greater than the available I Assuming thecollector-to-emitter saturation voltage of transistor Q4A to beapproximately 0.25 volt (VCESAT =0.25 volt) and its emitter to be at0.75 volt, the collector potential of transistor Q4A is approximately1.0 volt. In order for current to flow from the second emitter oftransistor Q2B, the potential at its base must exceed 3.1 volts (thepotential at the emitter of transistor QSA plus the V offset oftransistor Q5A plus the V of transistor QZB). Thus, since the basepotential of transistor 02B is maintained at 1.0 volt by the collectorof transistor Q4A, no current flows into the collectorto-emitter oftransistor QSA and its collector-to-emitter voltage is equal to the Voffset.

It is of importance to note at this point that in this steady statecondition, transistor QSA permits base-to-emitter current flow butprovides no collector-to-emitter current. Transistor 05A is thusoperated as a diode and there is no increase in power dissipation under,steady state conditions due to its presence. It should also be notedthat transistor QZB which provides the collector current to transistor05A is rendered nonconducting by means of the conduction of transistorQ4A in response to the amount of current generated by transistor QSA.

The emitter current of saturated transistor 04A is comprised of thecurrent through resistor R5 (I and the current through resistor R4 (I Iis approximately equal to the difference in potential between terminal10 (5 volts) and the base of transistor QSA (4XV divided by the ohmicvalue of R5, [V -4XV,, /R5]; and, I, is approximately equal to thedifference in potential between terminal 10 (5 volts) and the collectorvoltage of Q4A (Vna l'a' divided by the ohmic value of resistor R4,[V (VV )1 /R4-ll The emitter current of transistor Q4A provides tiie basedrive for transistors Q3 and 01A and the collector current to transistor08. The amount of current division between the bases of transistors 03and 01A is a function of the ratio of their areas and the ratio ofactual emitter currents. The division of base currents is controlled toensure that QlA is capable of sinking the variable load current intooutput terminal 20 which may, for example, range from 2.5 milliarnperesto 20 milliarnperes. Sufficient base drive must be applied to transistor01A to make sure that it is saturated when carrying the maximum ratedoutput load current which must be sunk. In addition to the base drive totransistor QlA sufficient base drive must be supplied to transistor Q3in order to cause it to saturate. The sum of these two base currentsplus the constant collector cur rent shunted by transistor Q8 issupplied by the emitter current of transistor Q4A. Transistor Q8, asmore fully set forth below, acts as a shunt path across thebase-to-emitter regions of transistors Q3 and QlA and due to AC couplinginto its base, causes transistors Q3 and 01A to turn off rapidly whenthe input signals go low.

The steady state collector current drawn by transistor O8 is determinedby the biasing circuit comprising resistor R9, diode connectedtransistor 09 and resistor R1. The current through resistor R9 (1 issubstantially equal to the difference in potential between V and the Vof transistor Q9 divided by the resistance of R9, [V V /R9]. Most ofthis current flows into the collector and base of transistor 09developing a potential which is applied across the series combinationcomprising resistor R1 and the base-to-emitter junction of transistorQ8. The current through resistor R1 and into the base of transistor O8is approximately equal to the difference in potential between thebase-to-emitter voltage of transistor 09 and the base-to-emitter voltageof transistor Q8 divided by the ohmic value of resistor R1; (VV,,,;,)/R1. (In addition to the difference in size, transistor Q9conducts more collector current than transistor Q8 and hence the V ofthe former will be greater than that of the latter.) The collectorcurrent of transistor Q8 (I may thus be adjusted to be a well definedratio of the collector current of transistor Q9 09)- In a circuitembodying the invention, was set to approximately 500 microamperes bymaking resistor R9 equal to 10 kilohms. Resistor R1 was selected to be aminimum of l Kohm to isolate (somewhat) the base of transistor Q8 fromthe base of transistor Q9. Transistor 08 was designed to ensure that,with R1 equal to l Kohm, the steady state value of I was approximatelyequal to one-half I 250 microamperes). Transistor Q8 thus sinks a smallsteady state current which results in a very efficient bias control andin minimal current waste.

With transistor Q4A conducting and saturated, the potential at the baseof transistor 02B is 1 volt. Assuming transistor Q3 also to be saturatedand its collector-to'emitter saturation voltage to be 0.2 volt, thecurrent flowing through resistors R2 and R8 is approximately 2.25milliarnperes. If, for'example, resistor R8 is ohms, the potential atthe first emitter 1e of transistor 028, which is common to the base oftransistor 02A, is approximately 0.425 volt. Under this condition, thebase of transistor 02B is forward biased with respect to its firstemitter by a potential of 0.575 volt. Since the threshold of thebase-to-emitter junction is 0.75 volt, transistor 02B is not biased intoconduction.

Maintaining the base-to-emitter potential of transistor 02B slightlybelow the turn on threshold is advantageous in that it permits veryrapid turn on of the transistor. Since most of the charge needed to turnon transistor 02B is stored during the steady state operation, littleadditional charge is required to turn it on completely (as describedbelow) and this minimizes its turn on time.

With transistors Q3 and 01A saturated, the base potential of transistorQZA is maintained at 0.425 volt and its emitter potential is equal tothe potential at output terminal 20 which is equal to the saturationvoltage of transistor 01A. The baseto-emitter potential of transistor02A is thus well below the 0.75-volt threshold and transistor Q2A,though forward biased, remains nonconducting.

Finally, it should be noted that for the steady state condition, thereis no conduction in or through the junctions forming transistors QlB,04B and QSB.

11. One or more of the input signals (applied to terminals 14 and 16)make a transition from the steady state high of 4 volts or more to a lowof 0.35 volt or less.

The negative-going transition at the input occurs very quickly and theresponse of the present circuit follows almost as rapidly. However, itis important for a better understanding of the operation and to bestappreciate the advantages of the circuit, to identify the sequence ofevents that occur in the circuit as the input signal switches'from high"to low."

First, when the input signal voltage reaches 2.25 volts, the current inresistor R5 ceases to flow into the base region of QSA and insteadbegins flowing through one or both of the input diodes CR1 and CR2(depending on which of the input signals has made the transition tolow). Assuming the threshold of diodes CR1 and CR2 to be 0.75 volt andrecalling that under steady state conditions the base of transistor QSAis at 3 volts (4V it follows that the current through R5 will flow intoCR1 or CR2 when the signal associated with their input terminal dropsbelow 2.25 volts.

Secondly, when the input signal reaches 1.5 volts, the baseto-emitterjunction of transistor 06 (V,, of transistor O6 is assumed to remain at2.25 volts during the input transition from 2.25 to l .5 volts) becomesforward biased and the emitter current of transistor QSA ceases to flowinto the base collector diode of transistor Q6. It is important to notethat the circuit thus exhibits a dual threshold characteristic. Thefirst threshold as described above occurs when one or both diodes CR1and CR2 begin conducting preventing further base drive into transistorQSA and the second threshold occurs when the base-to-emitter junction oftransistor Q6 begins conducting. The importance and usefulness of thisdual threshold characteristic is described subsequently.

The effectiveness of transistor O6 to switch the charge carriers from CS is not obvious, because no steady state current is supplied at thistime to its base (which ordinarily would be present in conventional'l'lL circuits). However, in this circuit, transient current providesbase current to transistor Q6 which causes transistor O6 to conduct as atransistor and therewith carry out its sweeping function with respect toC It is to be recalled that in the previous steady state condition whenthe base-emitter junctions of transistor Q6 are reverse biased,transistor Q6 has been in saturation with all its base current flowingto its collector. Transistors operating in this mode exhibit delaystimes of a few hundred picoseconds when a current is subsequently drawnfrom their emitters. Thus, when one or more of the base-emitterjunctions of transistor Q6 becomes forward biased, the charge stored inthe base collector junction is instantly available to provide currentinto the base. Additionally, as the input continues to fall from 1.5volts to 0.35 volt or less, the base of transistor Q6 falls concurrentlyfrom 2.25 volts to 1.10 volts or less, because one or more of itsbase-to-emitter regions is forward biased.

If it is assumed, for the instant, that the collector potential oftransistor Q6 were to be maintained at 1.5 volts, two capacitances wouldcontribute to the base drive of transistor 06. The stray base tosubstrate capacitance (not shown) and the collector-to-base capacitancewould provide their stored charge to the base of transistor 06 since thebase-to-emitter region of transistor Q6 provides a path for the flow oftheir charges. The base current in transistor Q6 causes a current toflow between the collector and emitter which is its forward currentratio (B) times the base current. The collector-toemitter current thussweeps out the charges present on C During this period there is oneaction that is detrimental to the performance of transistor Q6. That is,the stored base-toemitter charge of transistor QSA must be reduced tozero by flowing in the reverse direction through the base-to'emitter oftransistor Q6. However, it can be shown that the available forwardcharge exceeds the reverse charge by an adequate margin. In practice,measured waveforms at the collector of transistor O6 in the circuitembodying the invention are not discemibly different than those of astandard 'ITL circuit. Thus it has been shown that transistor Q6conducts current from its collector to its emitter in transistor fashionthereby rapidly removing or sweeping the charge stored at the base oftransistor Q4A and turning it off very quickly. It should also beappreciated that a signal transistor (O6) is connected between the baseof transistor Q4A and the input terminals. This assures that'whentransistor 06 conducts and saturates, a very low impedance or saturationvoltage is present between the base of Q4 and the input node.

The operation of transistor 06 may be further enhanced by means of theaddition of transistor 058 which is operated as a capacitor and whichcouples the rising potential at the collector of transistor QSA to thebase of transistor Q6. As the collector voltage of transistor QSAbecomes more positive (transistor QSA is being turned off and transistorQ4A is being turned off allowing 0213 whose base is connected throughresistor R4 to V to drive the collector of transistor QSA towards V morecharge is coupled to the base of transistor Q6 (driving it harder intoconduction) through the capacitance of the reverse biasedjunctions oftransistor 0513.

The cutoff of transistor Q4A is further aided by the stored charge oftransistors 03 and 01A since they maintain the emitter of transistor Q4Aat a positive potential which causes the base-to-emitter junction oftransistor Q4A to be momentarily reverse biased. This occurs since theemitter of transistor Q4A is momentarily held at 0.75 volt while itsbase voltage is equal to the low level (0.35 volt maximum) plus thesaturation voltage of transistor Q6 which may be assumed to be 0.3 voltmaximum for this condition.

' With the cutoff of transistor Q4A, no more current is supplied to thebases of transistors Q3 and QlA. The stored charge on the bases willnormally be removed by the collector current of forward biasedtransistor O8. in addition to the steady state bias the base oftransistor Q8 is also AC coupled to the collector of transistor Q4A bymeans of the capacitance of the reverse biased junctions of transistor048. As Q4A cuts off, its rise in collector voltage is AC coupled to thebase of transistor Q8. Transistor Q8 which was conducting a steady andrelatively constant current (250 microamperes) starts conductingadditional collector current immediately. The additional current whichtransistor 08 can carry is the AC current coupled through capacitor 048multiplied by the forward current ratio of transistor Q8. The decouplingprovided by resistor R1 now becomes important since its resistanceensures that the AC coupled current flows largely into the base of 08rather than being shunted into the collector of transistor Q9.Transistor Q8 conducts an increased collector current so long as thecollector potential of transistor Q4A rises and thus cuts offtransistors 01A and Q3 quickly and positively.

Concurrently with the rise in the collector voltage of transistor Q4A,transistor 02B is turned on. Transistor 02B is turned on very quicklysince only a slight positive increment in its base voltage is necessaryto turn it on. Transistor 0213 provides a current into the base oftransistor Q2A equal to its forward current ratio multiplied by the basecurrent available to it. There is negligible resistance limiting thecurrent flow between the emitter of transistor Q28 and the base oftransistor 02A which minimizes the turn on time of QZA. During the timethat transistors Q28 and QZA are turning on, the stored chargesassociated with transistors 01A and Q3 have been swept out by transistorQ8 reducing their collector current to zero.

Transistors 01A and Q3 are quickly turned off when transistor QZA isturned on to prevent undesirable power transients and the associatedincrease in power dissipation. Another major advantage of concurrentlyturning off 01A and turning on Q2A is that the total emitter current oftransistor Q2A is made available to charge the load capacitance whichrapidly drives the signal at output terminal 20 to the high state.

The output is also AC coupled to the base of Q8 by means of the reversebiased junctions of transistor 018. As the voltage at output terminal 20rises, the signal is fed back to the base of transistor Q8 whichconducts more current as described above. This increased current oftransistor Q8 offsets the effect of the Miller capacitance associatedwith the collector-to-base junction of transistor QlA. Thus, though therise in the collector voltage of transistor 01A is coupled back to itsbase by its collector-to-base capacitance, the increased conduction oftransistor Q8 efi'ectively prevents the additional charge from flowinginto the base of transistor QIA.

111. One or more inputs at a steady state low of 0.35 volt or less.Under this condition, steady state current flows through resistor R andthrough the anode to cathode junctions of these diodes (CR1, CR2) whoseinput signals are low. In addition, bias current flows through resistorR9 into the base of transistor ()8. The collector current of transistorQ8, as described above, shunts to ground any leakage current due totransistors Q4A, Q3 or QlA and therefore maintains transistors Q3 andQlA in the cutoff condition. With transistor Q3 cut off all base currentthat may be required to support the load current at the emitter oftransistor 02A flows through resistor R3 and into output terminal 20.

All other transistor junctions are nonconducting in this steady statecondition except for leakage currents which may be neglected. The powerdissipation for the steady state low" condition is thus minimized byusing a biasing scheme which draws very little current in the steadystate.

lV. Transition of all low inputs from 0.35 volt or less to 4.0.volts ormore. The transition of the input signals, as noted above, occurs withina few nanoseconds. However, the sequence or events as the voltageincreases are identifiable and are set forth to bring out more clearlythe operation of the circuit. First, the current through resistor R5starts transferring from the input diodes into the base of transistorQSA. Total current transfer of the current through resistor R5 does notoccur until the input voltage reaches 2.25 volts. However, the transferof some current starts immediately, with the positive going transitionof the input signal, since the emitter of transistor QSA is held at alow value of potential by various stray and shunt capacitances couplingit to the substrate and hence to ground potential.

It is important to note that the current available at the emitter oftransistor QSA to charge these capacitances is the available basecurrent multiplied by the forward current ratio of transistor QSA.During the transient interval following the positive going transition,the collector-to-second emitter of transistor Q2B provides a very lowimpedance between the collector of transistor QSA and the source ofpotential V That is, transistor Q2B can provide all the collectorcurrent that transistor QSA requires. Transistor 023 has thus changedfrom a very high impedance cutoff condition (described under I above) toa relatively low impedance (highly forward biased condition). The highconduction level of transistor QSA is an important feature of theconfiguration since it avoids undesirable delay in charging thecapacitance associated with the input of transistor Q4A. Thus the baseof Q4A reaches its required turn on threshold voltage (1.5 volts) veryrapidly. Transistor QSA continues to amplify the current generatedthrough current source resistor R5 and to apply the amplified current totransistor Q4A until the potential at the collector of the latter fallsbelow approximately 3 volts. At that point the collector potential oftransistor QSA tends to become lower than its emitter potential sincetransistor 028 is being cut off by the signal fed back from thecollector of transistor Q4A. There is thus a feedback arrangement whichcuts off the supply of collector current to transistor Q5A when itsemitter current causes the collector potential of transistor Q4A to fallbelow 3.0 volts. Following the charging transient, transistor QSA iseffectively turned into a diode since its collector supply is cut ofi.Transistor QSA thus provides an amplified current during the initialtransient period to ensure rapid turn on and a steady state current ofmuch lower amplitude thereafter. As the gate output is being switched inresponse to the increasing signal at the input terminaLthe collectorsupply of transistor QSA is cut off and the steady state power dissipation is reduced to a level typical of a much slower logic gate.

Another advantage of the circuit embodying the invention is theincreased noise immunity. The noise immunity levels of the gate may becalculated assuming that the maximum value of the low output is 0.35volt and the minimum value of the high output is 3.8 volts and recallingthat: (1) all input signals must make a positive going transition from alow (0.35 volt) to slightly more than a 2.25-volt threshold to reversebias the input diodes and cause the logic gate output at terminal 20 toswitch from a high (3.8 volts) to a low" (0.35 volt); and (2) at leastone input signal must make a negative going transition from a high" (3.8volts) to slightly less than the 2.25-volt threshold to forward bias theinput diodes (and to less than 1.5 volts to forward bias transistor O6to cause the logic gate output at terminal 20 to switch from a low (0.35volt) to a high (3.8 volts). It is evident that: (l) for the conditionof at least one input low, a positive going noise pulse applied to theinput terminal would have to exceed 1.9 volts (2.25 volts-0.35 volts)before initiating the sequence of events which cause the output 20 ofthe logic gate to switch from high to low; and (2) for the condition ofall inputs high a negative going noise pulse applied to the input wouldhave to exceed 1.55 volts (3.8 volts-2.25 volts) before initiating agradual response and exceed 2.3 volts 3.8 volts-1.5 volts) beforeinitiating the rapid sequence of events which cause the output 20 of thelogic gate to switch from low" to high."

In measurements on a circuit embodying the invention it was found thatthe threshold voltage at the base of transistor Q6 was 2.1 volts ascompared to the 2.25 volts used in the example above. The level of 2.1volts is reasonable since V is a function of the current therethroughand the temperature thereof and may vary considerably about the value of0.75 volt. Assuming the same limits on the low output (0.35 volt) andthe high output (3.8 volts), as above, the noise immunity level with theoutput low was found to be 1.75 volts for both highand low-frequencynoise signals,'and the high noise immunity level was found to be 1.7volts for low-frequency noise signals and 2.30 volts for high-frequencynoise signals (spikes).

The dual-threshold characteristic and its desirable effect on the noiseimmunity characteristics exhibited by the circuit are furtherillustrated by the response of the circuit to the following test.Measurements were made of the time required for the output to go from alow" level to 2 volts with the following results: (1 a negative-goingtransition from 4 volts to zero volt had to be applied to the input foronly 9 nanoseconds before the output reached 2 volts; (2) anegative-going transition from 4 volts to 1 volt had to be applied for17 nanoseconds in order to cause the output to switch from a low to 2volts; and (3) a negative pulse transition from 4 volts to 1 .5 voltshad to be applied for nanoseconds before the output goes from a low" tothe 2-volt level. It is thus evident that the input characteristicsrender the circuit relatively immune to noise pulses appearing on theinput lines.

It has thus been shown that the noise immunity of the gate may beincreased and that such increased noise immunity may be obtained withoutincreasing the power dissipation decreasing the speed, or reducing thefanout capability.

The transistors used in the embodiment shown in FIG. 3 are all of theNPN-type but it should be obvious that transistors of a different typeof comparable speed could also have been used.

What is claimed is:

1. In a logic circuit, in combination:

a first transistor having a collector, base and emitter;

a current source;

a second transistor having a collector, base and emitter, directlyconnected at its base to said current source and at its emitter to thebase of said first transistor, the baseto-emitter path of said secondtransistor being in the forward direction relative to the flow ofcurrent from said source;

an asymmetrically conducting device connected between the emitter ofsaid first transistor and the base of said second transistor, saiddevice being poled in the forward direction relative to the flow ofcurrent from said source;

a signal input terminal at said emitter of said first transistor;

and

means for applying a signal to said input terminal which, when of onevalue, is sufficient to forward bias said device for causing the currentfrom said current source to flow into said device and into said inputterminal, and when of second value is sufficient to reverse bias saiddevice and the emitter-to-base path of said first transistor for causingthe current from said current source to flow through the base to emitterpath of said second transistor and the base-to-collector path of saidfirst transistor.

2. In a logic circuit as set forth in claim 1, further including a thirdtransistor having a base, emitter and collector, the emitter of saidthird transistor being connected to the collector of said secondtransistor, and the collector of said third transistor being connectedto a source of operating potential poled in a direction to permit saidthird transistor to conduct current through its collector-to-emitterpath to said second transistor; and

means coupled to the base of said third transistor and responsive tosaid first transistor for controlling the state of said thirdtransistor.

3. The combination as claimed in claim 2 wherein said lastnamed meanscomprises a fourth transistor having collector, base and emitter,connected at its base to the collector of said first transistor andresponsive to base-to-collector current flow in said first transistorfor conducting and applying a signal to the base of said thirdtransistor for cutting the latter off.

4. The combination as claimed in claim 2, wherein said lastnamed meanscomprises a fourth transistor having a collector, base and emitter,connected at its base to the collector of said first transistor andresponsive to base-to-emitter current flow in said first transistor forbeing driven to cutoff and for applying a signal to the base of saidthird transistor for driving the latter into conduction.

5. in a logic circuit as set forth in claim 1, said asymmetricallyconducting device comprising a diode.

6. The combination as claimed in claim 5 further including:

first and second power terminals for a source of operating potential,and wherein said current source includes a resistor connected at one endto the base of said second transistor and at the other end to that oneof said two power terminals which is poled to forward bias thebaseto-emitter junction of said second transistor.

7. The combination as claimed in claim 6 further including a resistorconnected at one end to said signal input terminal and at the other endto that one of the two power terminals whose potential is in a directionto reverse bias said asymmetrically conducting device,

8. The combination as claimed in claim 3 further including at least onealternating current coupling element coupled between the collector ofsaid second transistor and the base of said first transistor responsiveto an abrupt change in potential at the collector of said secondtransistor for alternating current coupling a corresponding change involtage to the base of said first transistor.

The combination as claimed in claim 8 wherein said coupling elementcomprises a reverse biased semiconductor junction.

10. In a logic circuit, in combination:

a plurality of input signal terminals adapted to receive multivaluedsignals;

a transistor having a plurality of emitters each connected to adifferent one of said input terminals, a base, and a collector having acapacitance associated therewith;

a source of current;

current amplifying means, having a control electrode connected to saidsource of current, for amplifying the current from said current sourceand for supplying the amplified current to the base of said transistor,said amplified current flowing from the base-to-collector of saidtransistor for charging the capacitance associated therewith in responseto signals applied at said input terminals having a value to reversebias the base-to-emitter junctions of said transistor;

asymmetrically conducting means, connected between the control electrodeof said current-amplifying means and a different one of said inputterminals in a direction to easily conduct current from said controlelectrode to said input terminals, said asymmetrically conducting meansbeing responsive to signals having a first voltage level applied at saidinput terminals in a direction to forward bias one or more of theemitter-to-base junctions of said transistor for causing said currentsource current to flow through said asymmetrically conducting means andthereby preventing the further flow of current source current to saidamplifying means.

1. In a logic circuit, in combination: a first transistor having acollector, base and emitter; a current source; a second transistorhaving a collector, base and emitter, directly connected at its base tosaid current source and at its emitter to the base of said firsttransistor, the base-toemitter path of said second transistor being inthe forward direction relative to the flow of current from said source;an asymmetrically conducting device connected between the emitter ofsaid first transistor and the base of said second transistor, saiddevice being poled in the forward direction relative to the flow ofcurrent from said source; a signal input terminal at said emitter ofsaid first transistor; and means for applying a signal to said inputterminal which, when of one value, is sufficient to forward bias saiddevice for causing the current from said current source to flow intosaid device and into said input terminal, and when of second value issufficient to reverse bias said device and the emitter-tobase path ofsaid first transistor for causing the current from said current sourceto flow through the base to emitter path of said second transistor andthe base-to-collector path of said first transistor.
 2. In a logiccircuit as set forth in claim 1, further including a third transistorhaving a base, emitter and collector, the emitter of said thirdtransistor being connected to the collector of said second transistor,and the collector of said third transistor being connected to a sourceof operating potential poled in a direction to permit said thirdtransistor to conduct current through its collector-to-emitter path tosaid second transistor; and means coupled to the base of said thirdtransistor and responsive to said first transistor for controlling thestate of said third transistor.
 3. The combination as claimed in claim 2wherein said last-named means comprises a fourth transistor havingcollector, base and emitter, connected at its base to the collector ofsaid first transistor and responsive to base-to-collector current flowin said first transistor for conducting and applying a signal to thebase of said third transistor for cutting the latter off.
 4. Thecombination as claimed iN claim 2, wherein said last-named meanscomprises a fourth transistor having a collector, base and emitter,connected at its base to the collector of said first transistor andresponsive to base-to-emitter current flow in said first transistor forbeing driven to cutoff and for applying a signal to the base of saidthird transistor for driving the latter into conduction.
 5. In a logiccircuit as set forth in claim 1, said asymmetrically conducting devicecomprising a diode.
 6. The combination as claimed in claim 5 furtherincluding: first and second power terminals for a source of operatingpotential, and wherein said current source includes a resistor connectedat one end to the base of said second transistor and at the other end tothat one of said two power terminals which is poled to forward bias thebase-to-emitter junction of said second transistor.
 7. The combinationas claimed in claim 6 further including a resistor connected at one endto said signal input terminal and at the other end to that one of thetwo power terminals whose potential is in a direction to reverse biassaid asymmetrically conducting device.
 8. The combination as claimed inclaim 3 further including at least one alternating current couplingelement coupled between the collector of said second transistor and thebase of said first transistor responsive to an abrupt change inpotential at the collector of said second transistor for alternatingcurrent coupling a corresponding change in voltage to the base of saidfirst transistor.
 9. The combination as claimed in claim 8 wherein saidcoupling element comprises a reverse biased semiconductor junction. 10.In a logic circuit, in combination: a plurality of input signalterminals adapted to receive multivalued signals; a transistor having aplurality of emitters each connected to a different one of said inputterminals, a base, and a collector having a capacitance associatedtherewith; a source of current; current amplifying means, having acontrol electrode connected to said source of current, for amplifyingthe current from said current source and for supplying the amplifiedcurrent to the base of said transistor, said amplified current flowingfrom the base-to-collector of said transistor for charging thecapacitance associated therewith in response to signals applied at saidinput terminals having a value to reverse bias the base-to-emitterjunctions of said transistor; asymmetrically conducting means, connectedbetween the control electrode of said current-amplifying means and adifferent one of said input terminals in a direction to easily conductcurrent from said control electrode to said input terminals, saidasymmetrically conducting means being responsive to signals having afirst voltage level applied at said input terminals in a direction toforward bias one or more of the emitter-to-base junctions of saidtransistor for causing said current source current to flow through saidasymmetrically conducting means and thereby preventing the further flowof current source current to said amplifying means.